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Zhang He-Kun, Tian Xuan, He Jun-Peng, Song Zhe, Yu Qian-Qian, Li Liang, Li Ming, Zhao Lian-Cheng, Gao Li-Ming. Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation. Chinese Physics B, 2020, 29(3): 038501  
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Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation
Zhang He-Kun1, Tian Xuan2, He Jun-Peng1, Song Zhe2, Yu Qian-Qian2, Li Liang2, Li Ming1, Zhao Lian-Cheng1, Gao Li-Ming1, †
School of Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai 200240, China
SanDisk Info Tech Shanghai, Shanghai 200241, China

 

† Corresponding author. E-mail: liming.gao@sjtu.edu.cn

Project supported by the SanDisk Info Tech Shanghai, China and the Institute of Microelectronic Materials & Technology, School of Materials Science and Engineering, Shanghai Jiao Tong University, China.

Abstract

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon (MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling (TAT) model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ∼ 1018 cm−3 and trap energy ∼ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.

PACS: ;85.25.Hv;;85.40.-e;;85.35.Gv;
Keyword:;NAND flash reliability;;gate oxide traps;;trap-assisted tunneling;;TCAD simulation;
1. Introduction

NAND flash has become the mainstream of data storage due to its high density, low cost, and much lower latency than hard disk drive (HDD). The NAND flash has successfully transferred from two-dimension (2D) to three-dimension (3D), in order to keep reducing cost for one bit. However, the cell reliability becomes more challenging due to smaller cell size and complicated 3D NAND process.

Most of NAND flash use metal–oxide–nitride–oxide–silicon (MONOS) multiple layer as the memory cell, in whichthe high-k block oxide is placed between gate and charge trapped layer (CTL), and a very thin bandgap engineered oxide on the top of channel silicon serves as a tunneling layer. Electrons are injected into or rejected out of CTL through Fowler–Nordheim (FN) tunneling due to high electric field in tunneling layer.[1,2] The high electric field used for progra/erase cycles creates traps or defects in oxide layer, leading to cell degradation and causing reliability issues.[3,4] The effects of traps in aluminum oxide on the fast Vt shift, cell program/erase (P/E) operations, and data retention properties of TANOS flash memory have been investigated experimentally and analyticaly.[5,6] Data retention phenomena of NAND flash device relating to temperature, program pattern, and bake time have been studied by TCAD simulation.[7] However, the influence of traps on MONOS-structured memory cell by comprehensively considering the trap position, trap density, and trap energy has not yet been fully discussed, especially by taking advantage of TCAD device modeling.

In this work, Sentaurus TCAD is adopted to simulate the memory characteristics of MONOS-structured NAND flash by placing hole traps in oxide layers. The gate leakage current (Ig) is more intensely affected by the traps in blocking layer rather than tunneling layer. Besides, the influence of trap density (Nt) and trap energy (Et) on P/E speed and data retention properties are investigated by applying TAT model to the current transport. A specific trap profile (Nt ∼ 1018 cm−3 and Et = 1 eV) shows a 10-times higher program speed with good data retention properties.

2. Experimental methods

The device simulation and characterizations were performed with Sentaurus device. Figure 1 shows the diagram of MONOS cell, where a SiO2/SiON/SiO2 multilayer is composed of the tunneling layer, SiO2 layer between Si3N4 CTL and metal gate working as a blocking layer. The metal gate was made up of tungsten and a thin TiN layer, which is used to prevent tungsten from diffusing into oxide. The FN tunneling and direct tunneling were taken into account for electron tunneling during P/E operation. The current transport through the MONOS layer for gate leakage was simulated with the TAT model.[8,9] To include these mechanisms, several models were activated in the TCAD. Shockley–Read–Hall (SRH) recombination model was used to simulate recombination through deep defect levels in the gap;[10,11] mobility models including doping-dependent mobility degradation model and high field mobility saturation model were used to simulate the scattering of the carriers by charged impurity ions and the carrier drift velocity in high electric fields;[12–15] Poole–Frenkel model was used for the explanation of transport effects in dielectrics;[16–18] trap model was used to simulate single-energy level trap in Si3N4 layer; tunneling models including direct tunneling model and FN tunneling model were used to simulate main tunneling effects of this device and explain gate leakage current, etc.[19–21]

Fig. 1. Diagram of multilayer structure of MONOS cell.

The band diagram of MONOS layer is shown in Fig. 2. In TAT model, when forward bias for program was used, the traps in blocking oxide can serve as an intermediate site for electrons tunneling to the gate. Tunneling current was therefore strongly enhanced as the barrier near the trap decreased due to Poole–Frenkel effect.[22] Since there could exist traps in both blocking oxide and tunneling oxide, the TAT process of MONOS layer became more complex than the MOS structure. In this simulation, traps were placed in blocking layer and tunneling layer respectively with Nt ranging from 1 × 1016 cm−3 to 1 × 1021 cm−3 based on previous flash memory studies.[23–26] The studies have been reported on TAT model in flash memory with Et = 4 eV and on oxide trap influence with Et from 0 eV to 4 eV.[27–29] Thus, trap energy (Et) ranged from 0 eV to 4 eV under conduction band in this study. The program and erase speed were investigated by comparing trapped charge generation speed and dynamic Vt shift during P/E operation. The data retention properties at different trap profiles were also evaluated for device reliability.

Fig. 2. Band diagram of MONOS layer under different bias conditions (energy in units of eV) at (a) thermal equilibrium state and (b) program state.

Generally, higher temperature enhances gate leakage current and accelerates oxide breakdown because trap activation energy decreases as temperature increases.[30,31] Since this simulation mainly focus on the influence of trap concentration and trap energy, it was performed at room temperature (300 K).

3. Results and discussion
3.1. Leakage in program process

In order to study the influence of oxide traps on gate leakage, traps are placed in blocking or tunneling layer with trap energy of 2 eV. The gate leakage–gate bias (Ig–Vg) curves are obtained by ramping up Vg from 0 V to 27 V in 10−4 s as shown in Figs. 3(a) and 3(b). It is obvious that the traps in tunneling layer just slightly enhance Ig (smaller than 10−11 A even at high Vg), while the traps in blocking layer dramatically increase Ig after Nt exceeds 1 × 1019 cm−3. In the case of Nt below 1 × 1019 cm−3, the maximum values of Ig for the traps in blocking layer are still about 100 times larger than those for the traps in tunneling layer. The influence of trap energy on gate leakage is shown in Fig. 4. It shows that Ig decreases for deeper traps, because the tunneling-related capture rate has inversely exponential relationship with trap energy as reported previously.[32–35]

Fig. 3. Gate leakage currents varying with gate bias for (a) different trap densities in blocking layer at 2 eV and (b) different trap densities in tunneling layer at 2 eV.
Fig. 4. Gate leakage currents varying with gate bias for different trap energies (Nt = 1 × 1020 cm−3).

To explain these results, the electric field distribution with different trap profiles is simulated. Figure 5(a) shows the electric field distribution of the whole device. By placing hole traps in blocking layer, electric field is redistributed as shown in Fig. 5(b). Specifically, in program, electric field decreases across blocking layer but increases in CTL and tunneling layer. An opposite result is observed by placing traps in tunneling layer. Figure 6(a) shows the influence of trap density on electric field distribution. Higher trap density in the blocking layer more strongly reduces the electric field on it. For different trap energyies it is apparent that the shallow traps (Et = 2 eV) more significantly affect electric field than deep traps (Et = 4 eV) as indicated in Fig. 6(b). According to the empirical trap-assisted tunneling model based on SILC measurements, the TAT current can be written as

where ϕa is the activation energy, Ediel is the electric field in dielectric, and C is a constant. Clearly, Ig is directly proportional to Ediel. Apparently, the enhanced gate leakage does not result from the strong electric field, but possibly is caused by lower activation energy for TAT tunneling at higher trap density or smaller trap energy.

Fig. 5. (a) Electric field distribution of the whole device, and (b) plots of electric field across layers versus distance fron electrode.
Fig. 6. Electric field profile across MONOS layer versus distance from electrode by placing hole traps with (a) different trap densities, and (b) different trap energies.
3.2. Program speed

The redistributed electric field could affect cell program as well. The enhanced program speed, which is contributed by TAT in blocking layer as mentioned above, is clearly demonstrated in Fig. 7(a) by measuring Vt shift as a function of programming time. When Nt increases to 1 × 1018 cm−3, faster Vt ramping up is observed. Comparing with the saturated Vt of non-trap cell, Nt = 1 × 1018 cm−3 saved 10 × time to achieve the same Vt, as noted in Fig. 8(a). When trap density exceeds 1 × 1018 cm−3, program speed also increases at the initial stage, however, Vt ramping up speed decreases later because leakage current overwhelms the tunneling current. When Nt increases to 1 × 1020 cm−3, Vt intensely decreases after 1 μs due to higher TAT probability at higher Nt for electrons tunneling from CTL to gate, which is proved by the larger Ig in Fig. 3(a). The progress of trapped charge in CTL with gate bias is plotted in Fig. 7(b). The process is finished within 1 ms. Compared with non-trap cell, hole traps in blocking oxide can reduce the gate voltage for achieving the saturated trapped charge density. Specifically, 1 × 1020 cm−3 traps in blocking layer reduce the maximal Vt by about 4 V for a saturated charge density.

Fig. 7. (a) Plots of Vt shift versus program time at different trap densities, and (b) plots of trapped charge versus gate bias at different trap densities in program process.
Fig. 8. (a) Plots of Vt shift versus program time at different trap energies and (b) plots of trapped charge versus gate bias at different trap energies.

Besides, the influence of trap energy on program speed is investigate, and the results are shown in Fig. 8(a). For various trap energy, Et = 1 eV most strongly improved the program speed without Vt downshift at long program time. Again, we plot the progress of trapped charge in CTL with gate bias. An intermediate trap energy (Et = 1 eV–3 eV) speeds up the program process by ∼ 0.8 V decrement for program voltage as shown in Fig. 8(b). From the above result, the trap energy does not enhance the program speed as intensely as trap density.

3.3. Leakage in erase process

To investigate the erase process of the device with trap in blocking and tunneling layer, we apply voltage to gate from 0 V to −20 V with other settings being the same as those in program experiments. As we can see from Figs. 9(a) and 9(b), it is obvious that the traps in tunneling layer just slightly enhance Ig (smaller than 10−11 A even in high Vg), while the traps in blocking layer strongly increase Ig when Vg exceeds 12 V. After Nt exceeds 1 × 1019 cm−3, Ig becomes larger. In the case of traps in tunneling layer, electrons at metal gate are blocked by blocking layer. Therefore, the TAT process in blocking layer is very weak, so Ig is below 10−11 A. In the case of traps in blocking layer, when Vg exceeds 12 V, the TAT and FN tunneling are enhanced, so a large number of electrons tunnel to CTL. Since the traps in blocking layer will enhance the electric field of tunneling layer, which is proved by Fig. 6(a), the tunneling current through the tunneling layer will also be intensified. Therefore, the traps in blocking layer can significantly increase the gate leakage current.

Fig. 9. Gate leakage currents varying with gate bias under different trap conditions in erase process: (a) different trap densities in blocking layer at 2 eV and (b) different trap densities in tunneling layer at 2 eV.

Again, we simulate the influence of trap energy (Et = 1 eV–4 eV) on Ig and the results are shown in Fig. 10(a). It is found that the shallow traps (Et = 1 eV–2 eV) can significantly influence Ig, which indicates that shallow traps strongly reduce the activation energy for TAT, according to Eq. (1) or further confirmation, we plot the trapped charge density as a function of Vgate as indicated in Fig. 10(b). This figure shows that the trapped charge increases dramatically after Vgate has exceeded about 11 V in the case of traps in blocking layer. When Nt = 1 × 1020 cm−3, the trapped hole in CTL decreases compared with the scenario of lower trap density. This is because the enhanced TAT due to traps in blocking layer will make electrons from the gate easier to tunnel to CTL, which increases the possibility of electron–hole recombination, leading to lower trapped hole density in CTL. This result confirms the existence of trap assisted tunneling and its role in tunneling of erase process.

Fig. 10. (a) Gate leakage currents varying with gate bias in erase process at different trap energies, and (b) trapped charges changing with gate bias at different trap densities in erase process.
3.4. Erase speed

Also, erase speed is discussed. For erase process, we reduce the gate voltage from 0 V to −20 V and read the Vt of cell at t = 10−7 s, 10−6 s, 10−5 s, 10−4 s, 10−3 s. Then we read the Vt of device by applying 0.5 V to the drain and increasing the gate voltage from −2 V to 4 V.

As figure 11(a) shows, when Nt increases to 1 × 1019 cm−3 faster, the Vt shifting down is observed. The erase speed, when Nt reaches to 1 × 1020 cm−3, is extraordinarily high, more than 100 times that when Nt = 1 × 1018 cm−3. As discussed in Fig. 6(a), traps in blocking layer enhance the electric field in tunneling layer, thus enhancing the erase speed. As erase time increases, the trapped holes become saturated and erase speed decreases in t = 10−6 s–10−4 s. In Fig. 11(b), we show the influence of trap energy on erase speed. Generally, shallow traps (Et = 1 eV–3 eV) can improve the erase speed when trap density is high (Nt = 1 × 1019 cm−3 in Fig. 11). However, in the case of Et = 1 eV, Vt shifting down stops and begins to recover and even rams up in t = 10−6 s–10−4 s, resulting in degraded erase efficiency. This is because electrons tunneling from gate to CTL becomes much stronger than holes tunneling from channel to CTL. Therefore, more electrons accumulate in CTL and thus increase Vt. This indicates that the high trap density (> × 1019 cm−3) at shallow trap energy (∼ 1 eV) is fatal for erase operation due to large leakage current and low erase efficiency.

Fig. 11. The Vt shifts varying with erase time for (a) different trap densities and (b) different trap energies, respectively.
3.5. Data retention

Finally, the influence of gate oxide traps on data retention properties is investigated. We program the cell for 10−4 s in program retention experiment and erase the cell for 10−3 s in erase retention experiment. Then we read the Vt of device at t = 101 s–105 s by applying 0.5 V to drain and ramping up the gate voltage from −2 V to 4 V.

The Vt windows of various trap densities are compared with each other in Fig. 12(a). For trap densities ≤ 1 × 1018 cm−3, the initial Vt and final Vt window are barely affected. However, as Nt increases to 1 × 1019 cm−3, data retention is notably deteriorated. Specifically, erased Vt has more Vt loss than programmed one, because positive traps in blocking layer enhance electrons tunneling from substrate to CTL as demonstrated in Fig. 5(b). From the above results, data retention at trap density Nt < 1 × 1018 cm−3 is comparable to non-trap cell. Using fitting curve and extrapolation method, we obtain Vt window ∼ 5 V at t = 0 s and Vt window ∼ 4 V after 10 years.

Fig. 12. Retention characteristics of MONOS cell with (a) different trap densities, and (b) different trap energies in blocking layer.

For Nt = 1 × 1019 cm−3 at different Et values, Et = 1 eV shows the worst data retention property. For deeper traps (Et ≥ 2 eV), data retention property is recovered. Besides, erased Vt with more Vt loss can also be found, especially after 10−4 s, which means that data retention characteristic turns worse. Deeper traps can improve data retention compared with shallow traps because electrons tunneling through block oxide are intensely prevented, which is confirmed by the reduced gate leakage in Fig. 4. From the figure, we obtain Vt window ∼ 6 V at t = 0 s and Vt window ∼ 5 V at t = 105 s.

4. Conclusions

In this work, the influences of trap position, trap density, and trap energy on device characteristics of MONOS-structured NAND flash are investigated through TCAD simulation. It is found that traps in blocking layer significantly increase the gate leakage in both program and erase process due to stronger TAT process. Besides, traps in blocking layer increase the program speed and the erase speed in a short period (less than 1μs), but slows down cell program in long time range if trap density is over 1 × 1019 cm−3. Furthermore, for trap density ≥ 1 × 1019 cm−3, data retention is obviously weakened, especially after 104 s. From the simulation results, trap in blocking layer with a density of ∼ 1018 cm−3 at ∼ 1 eV can increase single cell program speed by 10 times and increase erase speed slightly, and retain a Vt window as large as 4 V after 10 years. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.

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